Bounded Model Checking for Timed Systems

Audemard, Gilles and Cimatti, Alessandro and Kornilowicz, Artur and Sebastiani, Roberto (2002) Bounded Model Checking for Timed Systems. UNSPECIFIED. (In Press)

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    Enormous progress has been achieved in the last decade in the verification of timed systems, making it possible to verify significant real-world protocols. An open challenge is the identification of fully symbolic verification techniques, able to deal effectively with the finite state component as well as with the timing aspects. In this paper we propose a new, symbolic verification technique that extends the Bounded Model Checking (BMC) approach for the verification of timed systems. The approach is based on the following ingredients. First, a BMC problem for timed systems is reduced to the satisfiability of a math-formula, i.e., a boolean combination of propositional variables and linear mathematical relations over real variables (used to represent clocks). Then, an appropriate solver, called MathSAT, is used to check the satisfiability of the math-formula. The solver is based on the integration of SAT techniques with some specialized decision procedures for linear mathematical constraints, and requires polynomial memory. Our methods allow for handling expressive properties in a fully-symbolic way. A preliminary experimental evaluation confirms the potential of the approach.

    Item Type: Departmental Technical Report
    Department or Research center: Information Engineering and Computer Science
    Subjects: Q Science > QA Mathematics > QA075 Electronic computers. Computer science
    Uncontrolled Keywords: formal verification, timed systems, model checking, SAT
    Additional Information: In Proc. 22nd Joint International Conference on Formal Techniques for Networked and Distributed Systems (FORTE 2002). Houston, TX, USA, November 2002. LNCS © Springer Verlag. To appear.
    Report Number: DIT-02-044
    Repository staff approval on: 21 Jan 2003

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